Using unsatisfiable cores to debug multiple design errors

Andre Suelflow, Goerschwin Fey, Roderick Paul Bloem, Rolf Drechsler

Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review

Original language	English
Title of host publication	Proceedings of the 18th ACM Great Lakes symposium on VLSI
Publisher	.
Pages	77-82
DOIs	https://doi.org/10.1145/1366110.1366131
Publication status	Published - 2008
Event	ACM Great Lakes Symposium on VLSI - Orlando, Fla., United States Duration: 4 May 2008 → 6 May 2008

Conference	ACM Great Lakes Symposium on VLSI
Country/Territory	United States
City	Orlando, Fla.
Period	4/05/08 → 6/05/08

Access to Document

Formal Methods for Design & Verification
Jacobs, S., Bloem, R., Könighofer, R., Könighofer, B., Khalimov, A., Hofferek, G. & Braud-Santoni, N.
1/02/08 → 15/07/19
Project: Research area

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