Using unsatisfiable cores to debug multiple design errors

Andre Suelflow, Goerschwin Fey, Roderick Paul Bloem, Rolf Drechsler

Research output: Chapter in Book/Report/Conference proceedingConference contributionResearchpeer-review

Original languageEnglish
Title of host publicationProceedings of the 18th ACM Great Lakes symposium on VLSI
Publisher.
Pages77-82
DOIs
Publication statusPublished - 2008
EventACM Great Lakes Symposium on VLSI - Orlando, Fla., United States
Duration: 4 May 20086 May 2008

Conference

ConferenceACM Great Lakes Symposium on VLSI
CountryUnited States
CityOrlando, Fla.
Period4/05/086/05/08

Cite this

Suelflow, A., Fey, G., Bloem, R. P., & Drechsler, R. (2008). Using unsatisfiable cores to debug multiple design errors. In Proceedings of the 18th ACM Great Lakes symposium on VLSI (pp. 77-82). .. https://doi.org/10.1145/1366110.1366131

Using unsatisfiable cores to debug multiple design errors. / Suelflow, Andre; Fey, Goerschwin; Bloem, Roderick Paul; Drechsler, Rolf.

Proceedings of the 18th ACM Great Lakes symposium on VLSI. ., 2008. p. 77-82.

Research output: Chapter in Book/Report/Conference proceedingConference contributionResearchpeer-review

Suelflow, A, Fey, G, Bloem, RP & Drechsler, R 2008, Using unsatisfiable cores to debug multiple design errors. in Proceedings of the 18th ACM Great Lakes symposium on VLSI. ., pp. 77-82, ACM Great Lakes Symposium on VLSI, Orlando, Fla., United States, 4/05/08. https://doi.org/10.1145/1366110.1366131
Suelflow A, Fey G, Bloem RP, Drechsler R. Using unsatisfiable cores to debug multiple design errors. In Proceedings of the 18th ACM Great Lakes symposium on VLSI. . 2008. p. 77-82 https://doi.org/10.1145/1366110.1366131
Suelflow, Andre ; Fey, Goerschwin ; Bloem, Roderick Paul ; Drechsler, Rolf. / Using unsatisfiable cores to debug multiple design errors. Proceedings of the 18th ACM Great Lakes symposium on VLSI. ., 2008. pp. 77-82
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