Using unsatisfiable cores to debug multiple design errors

Andre Suelflow, Goerschwin Fey, Roderick Paul Bloem, Rolf Drechsler

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Original languageEnglish
Title of host publicationProceedings of the 18th ACM Great Lakes symposium on VLSI
Publisher.
Pages77-82
DOIs
Publication statusPublished - 2008
EventACM Great Lakes Symposium on VLSI - Orlando, Fla., United States
Duration: 4 May 20086 May 2008

Conference

ConferenceACM Great Lakes Symposium on VLSI
CountryUnited States
CityOrlando, Fla.
Period4/05/086/05/08

Projects

Formal Methods for Design & Verification

Jacobs, S., Bloem, R., Könighofer, R., Könighofer, B., Khalimov, A., Hofferek, G. & Braud-Santoni, N.

1/02/0815/07/19

Project: Research area

Cite this

Suelflow, A., Fey, G., Bloem, R. P., & Drechsler, R. (2008). Using unsatisfiable cores to debug multiple design errors. In Proceedings of the 18th ACM Great Lakes symposium on VLSI (pp. 77-82). .. https://doi.org/10.1145/1366110.1366131