This chapter provides guidance for characterizing the soft failure robustness of ICs and boards and offers insight into different types of soft failures. It shows modeled soft failure scenarios, and illustrates counter measures. The chapter helps establish a systematic approach to understanding and handling electrostatic discharge (ESD)-induced soft failures. A weak relationship exists between system level soft failures and IC level testing, such as HBM, MM, CDM, and latch-up. Therefore no conclusions about the soft failure behavior of an IC should be drawn from these tests. A broader classification of soft failure times facilitates the understanding of soft failure scenarios. The following classification is suggested: in-band/out-of-band with respect to voltage; in-band/out-of-band with respect to pulse width; local vs distant errors; and amplified/non-amplified soft failures. The chapter concludes by identifying strategies for robust ESD design, detailing the IC and board information needed to implement these strategies.
|Titel||System Level ESD Co-Design|
|Herausgeber (Verlag)||Wiley-IEEE Computer Society Press|
|Publikationsstatus||Veröffentlicht - 1 Jan 2016|
ASJC Scopus subject areas
- !!Computer Science(all)