TLP IV characterization of a 40 nm CMOS IO protection concept in the powered state

Benjamin Orr, Krzysztof Domanski, Harald Gossner, David Pommerenke

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, the interaction between the ESD protection concept and a powered output driver in a 40 nm CMOS process are investigated and characterized by TLP. By using IO test chips designed for HBM and CDM validation, the IV behavior of the pin is measured with the driver placed into various states.

Original languageEnglish
Title of host publicationElectrical Overstress/Electrostatic Discharge Symposium Proceedings 2016, EOS/ESD 2016
PublisherESD Association
ISBN (Electronic)9781585372898
DOIs
Publication statusPublished - 14 Oct 2016
Externally publishedYes
Event38th Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2016 - Garden Grove (Anaheim), United States
Duration: 11 Sep 201616 Sep 2016

Publication series

NameElectrical Overstress/Electrostatic Discharge Symposium Proceedings
Volume2016-October
ISSN (Print)0739-5159

Conference

Conference38th Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2016
CountryUnited States
CityGarden Grove (Anaheim)
Period11/09/1616/09/16

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Orr, B., Domanski, K., Gossner, H., & Pommerenke, D. (2016). TLP IV characterization of a 40 nm CMOS IO protection concept in the powered state. In Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2016, EOS/ESD 2016 [7592566] (Electrical Overstress/Electrostatic Discharge Symposium Proceedings; Vol. 2016-October). ESD Association. https://doi.org/10.1109/EOSESD.2016.7592566