The use of high-speed logic makes modern electronic systems highly susceptible to electrostatic discharge (ESD). Because of their wider bandwidth, faster digital devices are more susceptible to high frequency ESD transient fields. In the analysis of ESD problems, an exact knowledge of the affected PINs and nets is essential for an optimal solution. A three dimensional ESD scanning system, which has been developed to record the ESD susceptibility map for a printed circuit board, is presented, and the mechanisms that the ESD event couples into the digital devices is studied.
|Title of host publication||Electromagnetic Compatibility 2004|
|Pages||343 - 348|
|Publication status||Published - 2004|
|Event||2004 IEEE International Symposium on Electromagnetic Compatibility: EMC 2004 - Santa Clara, United States|
Duration: 9 Aug 2004 → 13 Aug 2004
|Conference||2004 IEEE International Symposium on Electromagnetic Compatibility|
|Period||9/08/04 → 13/08/04|