Strong and Efficient Cache Side-Channel Protection using Hardware Transactional Memory

Daniel Gruss, Julian Lettner, Felix Schuster, Olga Ohrimenko, Istvan Haller, Manuel Costa

Research output: Chapter in Book/Report/Conference proceedingConference contributionResearchpeer-review

Abstract

Cache-based side-channel attacks are a serious problem in multi-tenant environments, for example, modern cloud data centers. We address this problem with Cloak, a new technique that uses hardware transactional memory to prevent adversarial observation of cache misses on sensitive code and data. We show that Cloak provides strong protection against all known cache-based side-channel attacks with low performance overhead. We demonstrate the efficacy of our approach by retrofitting vulnerable code with Cloak and experimentally confirming immunity against state-of-the-art attacks. We also show that by applying Cloak to code running inside Intel SGX enclaves we can effectively block information leakage through cache side channels from enclaves, thus addressing one of the main weaknesses of SGX.
Original languageEnglish
Title of host publication2017 Proceedings of the 26th USENIX Security Symposium
Publication statusPublished - 16 Aug 2017

Cite this

Gruss, D., Lettner, J., Schuster, F., Ohrimenko, O., Haller, I., & Costa, M. (2017). Strong and Efficient Cache Side-Channel Protection using Hardware Transactional Memory. In 2017 Proceedings of the 26th USENIX Security Symposium

Strong and Efficient Cache Side-Channel Protection using Hardware Transactional Memory. / Gruss, Daniel; Lettner, Julian; Schuster, Felix; Ohrimenko, Olga; Haller, Istvan; Costa, Manuel.

2017 Proceedings of the 26th USENIX Security Symposium. 2017.

Research output: Chapter in Book/Report/Conference proceedingConference contributionResearchpeer-review

Gruss, D, Lettner, J, Schuster, F, Ohrimenko, O, Haller, I & Costa, M 2017, Strong and Efficient Cache Side-Channel Protection using Hardware Transactional Memory. in 2017 Proceedings of the 26th USENIX Security Symposium.
Gruss D, Lettner J, Schuster F, Ohrimenko O, Haller I, Costa M. Strong and Efficient Cache Side-Channel Protection using Hardware Transactional Memory. In 2017 Proceedings of the 26th USENIX Security Symposium. 2017
Gruss, Daniel ; Lettner, Julian ; Schuster, Felix ; Ohrimenko, Olga ; Haller, Istvan ; Costa, Manuel. / Strong and Efficient Cache Side-Channel Protection using Hardware Transactional Memory. 2017 Proceedings of the 26th USENIX Security Symposium. 2017.
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