Sparse matrix assembly on the GPU through multiplication patterns

R. Zayer, M. Steinberger, H. P. Seidel

Research output: Chapter in Book/Report/Conference proceedingConference contributionResearchpeer-review

Original languageUndefined/Unknown
Title of host publication2017 IEEE High Performance Extreme Computing Conference (HPEC)
Pages1-8
Number of pages8
DOIs
Publication statusPublished - 1 Sep 2017

Keywords

  • data structures
  • graph theory
  • graphics processing units
  • linear algebra
  • mathematics computing
  • matrix multiplication
  • mesh generation
  • parallel processing
  • query processing
  • sparse matrices
  • GPU
  • assembled matrix
  • assembly performance
  • assembly problem
  • assembly step
  • basic linear algebra operations
  • elementary contributions
  • explicit matrix form
  • global graph connectivity
  • graphics hardware
  • lean unstructured mesh representation
  • memory storage requirements
  • mesh memory layout
  • mesh querying data structures
  • multiplication patterns
  • numerical solvers
  • numerical treatment
  • parallel computing hardware
  • sparse matrix assembly
  • sparse matrix-matrix multiplication
  • standard HPC platforms
  • variational problems
  • vectorization
  • Graphics processing units
  • Hardware
  • Matrices
  • Memory management
  • Sparse matrices
  • Standards

Cite this

Zayer, R., Steinberger, M., & Seidel, H. P. (2017). Sparse matrix assembly on the GPU through multiplication patterns. In 2017 IEEE High Performance Extreme Computing Conference (HPEC) (pp. 1-8) https://doi.org/10.1109/HPEC.2017.8091057