Simple D flip-flop behavioral model of ESD immunity for use in the ISO 10605 standard

Guangyao Shen, Victor Khilkevich, Sen Yang, David Pommerenke, Hermann Aichele, Dirk Eichel, Christoph Keller

Research output: Contribution to journalConference article

Abstract

As the ESD stress is becoming more and more important for integrated circuits (ICs), the ability to predict IC failures becomes critical. In this paper, an 18 MHz D flip-flop IC is characterized and its behavioral model is presented. The resulting IC model is validated in the setup according to the ISO 10605 standard. A complete model of the setup combining the IC behavioral model and the passive parts of the setup is built to estimate the failure prediction accuracy in a totally simulated environment. The results show that the model can predict the triggering level with the error of less than 20%.

Original languageEnglish
Article number6899015
Pages (from-to)455-459
Number of pages5
JournalIEEE International Symposium on Electromagnetic Compatibility
Volume2014-September
Issue numberSeptember
DOIs
Publication statusPublished - 15 Sep 2014
Externally publishedYes
Event2014 IEEE International Symposium on Electromagnetic Compatibility: EMC 2014 - Raleigh, United States
Duration: 3 Aug 20148 Aug 2014

ASJC Scopus subject areas

  • Condensed Matter Physics
  • Electrical and Electronic Engineering

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