Abstract
As the ESD stress is becoming more and more important for integrated circuits (ICs), the ability to predict IC failures becomes critical. In this paper, an 18 MHz D flip-flop IC is characterized and its behavioral model is presented. The resulting IC model is validated in the setup according to the ISO 10605 standard. A complete model of the setup combining the IC behavioral model and the passive parts of the setup is built to estimate the failure prediction accuracy in a totally simulated environment. The results show that the model can predict the triggering level with the error of less than 20%.
| Original language | English |
|---|---|
| Article number | 6899015 |
| Pages (from-to) | 455-459 |
| Number of pages | 5 |
| Journal | IEEE International Symposium on Electromagnetic Compatibility |
| Volume | 2014-September |
| Issue number | September |
| DOIs | |
| Publication status | Published - 15 Sep 2014 |
| Externally published | Yes |
| Event | 2014 IEEE International Symposium on Electromagnetic Compatibility, EMC 2014 - Raleigh, United States Duration: 3 Aug 2014 → 8 Aug 2014 |
ASJC Scopus subject areas
- Condensed Matter Physics
- Electrical and Electronic Engineering
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Cite this
Shen, G., Khilkevich, V., Yang, S., Pommerenke, D., Aichele, H., Eichel, D., & Keller, C. (2014). Simple D flip-flop behavioral model of ESD immunity for use in the ISO 10605 standard. IEEE International Symposium on Electromagnetic Compatibility, 2014-September(September), 455-459. [6899015]. https://doi.org/10.1109/ISEMC.2014.6899015