Signal and Timing Analysis of a Phase-Domain All-Digital Phase-Locked Loop with Reference Retiming Mechanism

Stefan Mendel, Christian Vogel, Nicola Da Dalt

Research output: Chapter in Book/Report/Conference proceedingConference contributionResearchpeer-review

Original languageEnglish
Title of host publication16th International Conference on Mixed Design of Integrated Circuits and Systems
Publisher.
Pages681-687
Publication statusPublished - 2009
EventInternational Conference on Mixed Design of Integrated Circuits and Systems - Lodz, Poland
Duration: 25 Jun 200927 Jun 2009

Conference

ConferenceInternational Conference on Mixed Design of Integrated Circuits and Systems
CountryPoland
CityLodz
Period25/06/0927/06/09

Cite this

Mendel, S., Vogel, C., & Da Dalt, N. (2009). Signal and Timing Analysis of a Phase-Domain All-Digital Phase-Locked Loop with Reference Retiming Mechanism. In 16th International Conference on Mixed Design of Integrated Circuits and Systems (pp. 681-687). ..

Signal and Timing Analysis of a Phase-Domain All-Digital Phase-Locked Loop with Reference Retiming Mechanism. / Mendel, Stefan; Vogel, Christian; Da Dalt, Nicola.

16th International Conference on Mixed Design of Integrated Circuits and Systems. ., 2009. p. 681-687.

Research output: Chapter in Book/Report/Conference proceedingConference contributionResearchpeer-review

Mendel, S, Vogel, C & Da Dalt, N 2009, Signal and Timing Analysis of a Phase-Domain All-Digital Phase-Locked Loop with Reference Retiming Mechanism. in 16th International Conference on Mixed Design of Integrated Circuits and Systems. ., pp. 681-687, International Conference on Mixed Design of Integrated Circuits and Systems, Lodz, Poland, 25/06/09.
Mendel S, Vogel C, Da Dalt N. Signal and Timing Analysis of a Phase-Domain All-Digital Phase-Locked Loop with Reference Retiming Mechanism. In 16th International Conference on Mixed Design of Integrated Circuits and Systems. . 2009. p. 681-687
Mendel, Stefan ; Vogel, Christian ; Da Dalt, Nicola. / Signal and Timing Analysis of a Phase-Domain All-Digital Phase-Locked Loop with Reference Retiming Mechanism. 16th International Conference on Mixed Design of Integrated Circuits and Systems. ., 2009. pp. 681-687
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