An open-loop feedback-less CMOS multiphase generator circuit architecture is presented. The principle generates n 360◦/n-spaced outputs from a single-ended input LO or clock at the very same frequency. The phase accuracy of the implemented circuit employing the principle, relies on the matching of delays and weighted linear phase interpolation. The presented circuit is designed in a 28 nm bulk-CMOS technology covering an operating frequency range from 1.5 GHz up to 2.5 GHz. Simulation results of the designed multiphase generator show a worst case phase noise performance of −151 dBc/Hz at 100 MHz offset with a typical power consumption of only 3.5 mW from a 0.95 V supply at 2 GHz, demonstrating the feasibility of the presented circuit architecture.