Proving SIFA Protection of Masked Redundant Circuits

Research output: Chapter in Book/Report/Conference proceedingConference paperpeer-review

Abstract

Implementation attacks like side-channel and fault attacks pose a considerable threat to cryptographic devices that are physically accessible by an attacker. As a consequence, devices like smart cards implement corresponding countermeasures like redundant computation and masking. Recently, statistically ineffective fault attacks (SIFA) were shown to be able to circumvent these classical countermeasure techniques. We present a new approach for verifying the SIFA protection of arbitrary masked implementations in both hardware and software. The proposed method uses Boolean dependency analysis, factorization, and known properties of masked computations to show whether the fault detection mechanism of redundant masked circuits can leak information about the processed secret values. We implemented this new method in a tool called Danira, which can show the SIFA resistance of cryptographic implementations like AES S-Boxes within minutes.
Original languageEnglish
Title of host publicationAutomated Technology for Verification and Analysis
Subtitle of host publication19th International Symposium, ATVA 2021
PublisherSpringer
Number of pages16
Publication statusAccepted/In press - 2021
Event19th International Symposium on Automated Technology for Verification and Analysis : ATVA 2021 - Virtuell, Australia
Duration: 18 Oct 202122 Oct 2021

Conference

Conference19th International Symposium on Automated Technology for Verification and Analysis
Abbreviated titleATVA 2021
Country/TerritoryAustralia
CityVirtuell
Period18/10/2122/10/21

Keywords

  • SIFA
  • verification
  • hardware security

ASJC Scopus subject areas

  • Hardware and Architecture
  • Computer Science (miscellaneous)

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