Integrated circuits (ICs) sometimes fail when their power supply is disrupted by external noise, such as might occur during an electrical fast transient (EFT). A delay model was proposed in  which can be used to predict the variations in the delays through logic circuits caused by electromagnetic induced noise in the power supply voltage. This model is relatively simple and requires few parameters, giving it the potential to be used even when the IC is a 'black bos' and little information is available about the inner circuits. While design information might be approximated through testing, critical process characteristics may not be available which are needed for accurate results. The parameter of greatest concern is the velocity saturation index, since this parameter can exponentially increase the impact of power supply noise on delay. This paper describes an investigation of the sensitivity of the delay model in  to the velocity saturation index. Results indicate that the estimated delay, found while treating much of the circuit as a black box, is largely insensitive to the velocity saturation index. This result suggests that this model can be used effectively for prediction of electromagnetically-induced delay errors, even when limited process or circuit information is known.