Power Analysis Resistant Logic Styles - Design, Implementation, and Evaluation

Mario Kirschbaum

Research output: ThesisDoctoral Thesis

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  • Finished

    EU - TAMPRES - TAMper Resistant Sensor node

    Hutter, M., Kirschbaum, M., Plos, T., Korak, T., Wenger, E. & Schmidt, J.

    1/10/1030/09/13

    Project: Research project

  • FWF - IIA - Investigation of Implementation Attacks

    Wenger, E., Kirschbaum, M. & Schmidt, J.

    1/03/1030/11/12

    Project: Research project

  • IMPA Lab

    Posch, R., Rijmen, V., Posch, K., Kirschbaum, M., Schmidt, J., Schläffer, M., Szekely, A., Medwed, M., Plos, T., Peßl, P., Aigner, M. J., Wenger, E., Dominikus, S., Feldhofer, M., Hutter, M. & Oswald, M. E.

    1/10/9915/07/19

    Project: Research area

  • VLSI Design

    Medwed, M., Wenger, E., Aigner, M. J., Posch, K., Hutter, M., Kirschbaum, M., Schmidt, J., Posch, R., Dominikus, S., Szekely, A., Feldhofer, M. & Plos, T.

    1/01/9515/07/19

    Project: Research area