Modelling of equivalent channel dimensions of enclosed-layout transistors, integrated on 180 nm MiAMoRE test chip

Research output: Contribution to conferencePoster

Abstract



Original languageEnglish
Publication statusPublished - 2017
EventThe 13th International School on the Effects of Radiation on Embedded Systems for Space Applications - Leibniz Rechenzentrum, Garching, Germany
Duration: 23 Oct 201726 Oct 2017
Conference number: 13
https://seressa.in.tum.de/

Workshop

WorkshopThe 13th International School on the Effects of Radiation on Embedded Systems for Space Applications
Abbreviated titleSERESSA 2017
CountryGermany
CityGarching
Period23/10/1726/10/17
Internet address

Keywords

  • Total Ionizing Dose
  • MOS
  • X-ray
  • Integrated circuits

Fields of Expertise

  • Information, Communication & Computing

Fingerprint Dive into the research topics of 'Modelling of equivalent channel dimensions of enclosed-layout transistors, integrated on 180 nm MiAMoRE test chip'. Together they form a unique fingerprint.

  • Activities

    • 1 Poster presentation

    Modelling of equivalent channel dimensions of enclosed-layout transistors, integrated on 180nm MiAMoRE test chip

    Varvara Bezhenova (Speaker), Alicja Malgorzata Michalowska-Forsyth (Speaker)
    23 Oct 201726 Oct 2017

    Activity: Talk or presentationPoster presentationScience to science

    Cite this

    Bezhenova, V., & Michalowska-Forsyth, A. M. (2017). Modelling of equivalent channel dimensions of enclosed-layout transistors, integrated on 180 nm MiAMoRE test chip. Poster session presented at The 13th International School on the Effects of Radiation on Embedded Systems for Space Applications, Garching, Germany.