Modeling Timing Variations in Digital Logic Circuits Due to Electrical Fast Transients

Xu Gao, Chunchun Sui, Daryl G. Beetner, Sameer Hemmady, Joey Rivera, Susumu Yakura, Julio Villafuerte, David Johannes Pommerenke

Research output: Chapter in Book/Report/Conference proceedingConference contributionResearchpeer-review

Abstract

Integrated circuits (ICs) sometimes fail when their power supply is disrupted by external noise, like an electrical fast transient (EFT). Soft failures in these cases are often caused by timing errors in the IC, for example when delays through logic become too large to meet internal timing constraints. Methods are needed to predict when these failures will occur. A closed-form expression is proposed in this paper to predict the change in propagation delay through logic as a result of an EFT on the IC power supply. The expression uses process parameters that can be found from SPICE models of FETs within the IC or through external measurements of the IC when SPICE models are unavailable. The model is used to predict the frequency of a CMOS ring oscillator manufactured in 0.5 um technology. Predicted results closely match those found through measurements with a maximum relative error of approximately 1%.
Original languageEnglish
Title of host publication2013 IEEE International Symposium on Electromagnetic Compatibility
Pages484-488
DOIs
Publication statusPublished - 2013
Externally publishedYes

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Gao, X., Sui, C., Beetner, D. G., Hemmady, S., Rivera, J., Yakura, S., ... Pommerenke, D. J. (2013). Modeling Timing Variations in Digital Logic Circuits Due to Electrical Fast Transients. In 2013 IEEE International Symposium on Electromagnetic Compatibility (pp. 484-488) https://doi.org/10.1109/ISEMC.2013.6670461