Improvement of SPICE based ESD Protection Models for I/O Protection Modeling

Amin Pak; Seyed Mostafa Mousavi; David Pommerenke; Giorgi Maghlakelidze; Yang Xu

doi:10.1109/EMC/SI/PI/EMCEurope52599.2021.9559224

Improvement of SPICE based ESD Protection Models for I/O Protection Modeling

Amin Pak, Seyed Mostafa Mousavi, David Pommerenke, Giorgi Maghlakelidze, Yang Xu

Institute of Electronics (4390)

Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review

Abstract

Modeling ESD protection using the System Efficient ESD Design (SEED) methodology enables optimal protection of an IO using TVS and external components. The success of modeling depends on the accuracy of the models. This work shows improvements to SPICE models used to characterize TVS diodes and IC I/O. The improvement is twofold. The transition phases between snapback and main current flow have been adjusted to achieve realistic waveforms for the rise times from 500 ps to 5 ns in a voltage range from Vt1 to the high current region, and complex curvatures of the IV curve are included. The model is capable of operating in generic SPICE and being tested in ADS and LT-SPICE. The paper explains this in detail to enable the reader to apply this modeling principle.

Original language	English
Title of host publication	2021 Joint IEEE International Symposium on Electromagnetic Compatibility Signal and Power Integrity, and EMC Europe, EMC/SI/PI/EMC Europe 2021
Publisher	IEEE Publications
Pages	1006-1011
Number of pages	6
ISBN (Electronic)	9781665448888
ISBN (Print)	978-1-6654-4889-5
DOIs	https://doi.org/10.1109/EMC/SI/PI/EMCEurope52599.2021.9559224
Publication status	Published - 26 Jul 2021
Event	2021 Joint IEEE International Symposium on Electromagnetic Compatibility Signal and Power Integrity, and EMC Europe: EMC/SI/PI/EMC Europe 2021 - Raleigh, United States Duration: 26 Jul 2021 → 20 Aug 2021

Conference

Conference	2021 Joint IEEE International Symposium on Electromagnetic Compatibility Signal and Power Integrity, and EMC Europe
Abbreviated title	EMC/SI/PI/EMC Europe 2021
Country/Territory	United States
City	Raleigh
Period	26/07/21 → 20/08/21

Keywords

electrostatic discharge (ESD)
TVS
ESD protection
SPICE
Electrostatic discharge
SEED

ASJC Scopus subject areas

Aerospace Engineering
Safety, Risk, Reliability and Quality
Signal Processing
Energy Engineering and Power Technology
Radiation
Electrical and Electronic Engineering

Access to Document

10.1109/EMC/SI/PI/EMCEurope52599.2021.9559224

https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9559224

Cite this

Pak, A., Mousavi, S. M., Pommerenke, D., Maghlakelidze, G., & Xu, Y. (2021). Improvement of SPICE based ESD Protection Models for I/O Protection Modeling. In 2021 Joint IEEE International Symposium on Electromagnetic Compatibility Signal and Power Integrity, and EMC Europe, EMC/SI/PI/EMC Europe 2021 (pp. 1006-1011). Article 9559224 IEEE Publications. https://doi.org/10.1109/EMC/SI/PI/EMCEurope52599.2021.9559224

Improvement of SPICE based ESD Protection Models for I/O Protection Modeling. / Pak, Amin; Mousavi, Seyed Mostafa; Pommerenke, David et al.
2021 Joint IEEE International Symposium on Electromagnetic Compatibility Signal and Power Integrity, and EMC Europe, EMC/SI/PI/EMC Europe 2021. IEEE Publications, 2021. p. 1006-1011 9559224.

Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review

Pak, A, Mousavi, SM, Pommerenke, D, Maghlakelidze, G & Xu, Y 2021, Improvement of SPICE based ESD Protection Models for I/O Protection Modeling. in 2021 Joint IEEE International Symposium on Electromagnetic Compatibility Signal and Power Integrity, and EMC Europe, EMC/SI/PI/EMC Europe 2021., 9559224, IEEE Publications, pp. 1006-1011, 2021 Joint IEEE International Symposium on Electromagnetic Compatibility Signal and Power Integrity, and EMC Europe, Raleigh, United States, 26/07/21. https://doi.org/10.1109/EMC/SI/PI/EMCEurope52599.2021.9559224

Pak A, Mousavi SM, Pommerenke D, Maghlakelidze G, Xu Y. Improvement of SPICE based ESD Protection Models for I/O Protection Modeling. In 2021 Joint IEEE International Symposium on Electromagnetic Compatibility Signal and Power Integrity, and EMC Europe, EMC/SI/PI/EMC Europe 2021. IEEE Publications. 2021. p. 1006-1011. 9559224 doi: 10.1109/EMC/SI/PI/EMCEurope52599.2021.9559224

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title = "Improvement of SPICE based ESD Protection Models for I/O Protection Modeling",

abstract = "Modeling ESD protection using the System Efficient ESD Design (SEED) methodology enables optimal protection of an IO using TVS and external components. The success of modeling depends on the accuracy of the models. This work shows improvements to SPICE models used to characterize TVS diodes and IC I/O. The improvement is twofold. The transition phases between snapback and main current flow have been adjusted to achieve realistic waveforms for the rise times from 500 ps to 5 ns in a voltage range from Vt1 to the high current region, and complex curvatures of the IV curve are included. The model is capable of operating in generic SPICE and being tested in ADS and LT-SPICE. The paper explains this in detail to enable the reader to apply this modeling principle.",

keywords = "electrostatic discharge (ESD), TVS, ESD protection, SPICE, Electrostatic discharge, SEED",

author = "Amin Pak and Mousavi, {Seyed Mostafa} and David Pommerenke and Giorgi Maghlakelidze and Yang Xu",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 2021 Joint IEEE International Symposium on Electromagnetic Compatibility Signal and Power Integrity, and EMC Europe : EMC/SI/PI/EMC Europe 2021, EMC/SI/PI/EMC Europe 2021 ; Conference date: 26-07-2021 Through 20-08-2021",

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AU - Pak, Amin

AU - Mousavi, Seyed Mostafa

AU - Pommerenke, David

AU - Maghlakelidze, Giorgi

AU - Xu, Yang

PY - 2021/7/26

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N2 - Modeling ESD protection using the System Efficient ESD Design (SEED) methodology enables optimal protection of an IO using TVS and external components. The success of modeling depends on the accuracy of the models. This work shows improvements to SPICE models used to characterize TVS diodes and IC I/O. The improvement is twofold. The transition phases between snapback and main current flow have been adjusted to achieve realistic waveforms for the rise times from 500 ps to 5 ns in a voltage range from Vt1 to the high current region, and complex curvatures of the IV curve are included. The model is capable of operating in generic SPICE and being tested in ADS and LT-SPICE. The paper explains this in detail to enable the reader to apply this modeling principle.

AB - Modeling ESD protection using the System Efficient ESD Design (SEED) methodology enables optimal protection of an IO using TVS and external components. The success of modeling depends on the accuracy of the models. This work shows improvements to SPICE models used to characterize TVS diodes and IC I/O. The improvement is twofold. The transition phases between snapback and main current flow have been adjusted to achieve realistic waveforms for the rise times from 500 ps to 5 ns in a voltage range from Vt1 to the high current region, and complex curvatures of the IV curve are included. The model is capable of operating in generic SPICE and being tested in ADS and LT-SPICE. The paper explains this in detail to enable the reader to apply this modeling principle.

KW - electrostatic discharge (ESD)

KW - TVS

KW - ESD protection

KW - SPICE

KW - Electrostatic discharge

KW - SEED

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BT - 2021 Joint IEEE International Symposium on Electromagnetic Compatibility Signal and Power Integrity, and EMC Europe, EMC/SI/PI/EMC Europe 2021

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Y2 - 26 July 2021 through 20 August 2021

ER -

Improvement of SPICE based ESD Protection Models for I/O Protection Modeling

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Keywords

ASJC Scopus subject areas

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