Abstract
Electrostatic Discharge (ESD) generators are used for testing the robustness of electronics towards ESD. Most generators are built in accordance with the IEC 61000-4-2 specifications. It is shown that the voltage induced in a small loop correlates with the failure level observed in an ESD failure test on the systems comprising fast CMOS devices, while rise time and current derivative of the discharge current did not correlate well. The electric parameters are compared for typical and modified ESD generators and the effect on the failure level of fast CMOS electronics is investigated. The consequences of aligning an ESD standard with the suggestions of this paper are discussed with respect to reproducibility and test severity.
Original language | English |
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Pages (from-to) | 52-57 |
Number of pages | 6 |
Journal | IEEE International Symposium on Electromagnetic Compatibility |
Volume | 1 |
Publication status | Published - 20 Oct 2003 |
Externally published | Yes |
Event | 2003 IEEE Symposium on Electromagnetic Compatibility - Boston, MA, United States Duration: 18 Aug 2003 → 22 Aug 2003 |
Keywords
- ESD generator
- Fast CMOS system
- Induced loop voltage
ASJC Scopus subject areas
- Condensed Matter Physics
- Electrical and Electronic Engineering