Impact of ESD generator parameters on failure level in fast CMOS system

Kai Wang, David Pommerenke*, Ramachandran Chundru, Jiusheng Huang, Kai Xiao, Ponniah Ilavarasan, Mike Schaffer

*Corresponding author for this work

Research output: Contribution to journalConference article

Abstract

Electrostatic Discharge (ESD) generators are used for testing the robustness of electronics towards ESD. Most generators are built in accordance with the IEC 61000-4-2 specifications. It is shown that the voltage induced in a small loop correlates with the failure level observed in an ESD failure test on the systems comprising fast CMOS devices, while rise time and current derivative of the discharge current did not correlate well. The electric parameters are compared for typical and modified ESD generators and the effect on the failure level of fast CMOS electronics is investigated. The consequences of aligning an ESD standard with the suggestions of this paper are discussed with respect to reproducibility and test severity.

Original languageEnglish
Pages (from-to)52-57
Number of pages6
JournalIEEE International Symposium on Electromagnetic Compatibility
Volume1
Publication statusPublished - 20 Oct 2003
Externally publishedYes
Event2003 IEEE Symposium on Electromagnetic Compatibility - Boston, MA, United States
Duration: 18 Aug 200322 Aug 2003

Keywords

  • ESD generator
  • Fast CMOS system
  • Induced loop voltage

ASJC Scopus subject areas

  • Condensed Matter Physics
  • Electrical and Electronic Engineering

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