High-Speed RSA Hardware Based on Barret's Modular Reduction Method

Johann Großschädl

Research output: Chapter in Book/Report/Conference proceedingConference contributionResearchpeer-review

Original languageEnglish
Title of host publicationCryptographic Hardware and Embedded Systems — CHES 2000
EditorsÇetin K. Koç, Christof Paar
Place of PublicationBerlin
PublisherSpringer Verlag
Pages191-203
Volume1965
ISBN (Print)3-540-41455-X
Publication statusPublished - 2000
EventCHES - Worcester, MA, United States
Duration: 17 Aug 200018 Aug 2000

Publication series

NameLecture Notes in Computer Science
PublisherSpringer Verlag

Conference

ConferenceCHES
CountryUnited States
CityWorcester, MA
Period17/08/0018/08/00

Treatment code (Nähere Zuordnung)

  • Application
  • Experimental

Cite this

Großschädl, J. (2000). High-Speed RSA Hardware Based on Barret's Modular Reduction Method. In Ç. K. Koç, & C. Paar (Eds.), Cryptographic Hardware and Embedded Systems — CHES 2000 (Vol. 1965, pp. 191-203). (Lecture Notes in Computer Science). Berlin: Springer Verlag.