The growth of the cyber-physical systems (CPSs) and the Internet of Things (IoT) in terms of functionality, connectivity, diversity, and size has been significant in the last years. The number of low-cost embedded devices in the field has dramatically increased and even though they enhance our lives in many ways, at the same time they are becoming attractive target for cybercriminals. The variety of these devices makes them vulnerable to new attacks, making the security challenges bigger and more diverse than ever, especially if no protection mechanism are offered. In this work we present a hardware/software co-designed memory protection approach that provides efficient software isolation of tasks, including a novel solution based on an existing concept for fine-grained protection of shared on-chip peripherals. The security extensions are implemented into a RISC-V-based microcontroller and a microkernel-based operating system, have small hardware and software footprint, and do not produce big runtime overhead.
|Title of host publication||2019 IEEE International Conference on Industrial Cyber Physical Systems (ICPS)|
|Publisher||Institute of Electrical and Electronics Engineers|
|Publication status||Published - 2019|
Malenko, M., & Baunach, M. C. (2019). Hardware/Software Co-designed Peripheral Protection in Embedded Devices. In 2019 IEEE International Conference on Industrial Cyber Physical Systems (ICPS) (pp. 790-795). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ICPHYS.2019.8780325