Abstract
While developing embedded devices a significant challenge is to choose the appropriate computing architecture. Especially during early design stages providing measurable metric on the performance demands to implement a specified algorithm is required. Usually this includes a large amount of target dependency, like the chosen micro-controller platform. This work aims on providing a generalized method to estimate the processing time of a dedicated algorithm, when being run on a variety of hardware choices. The focus is on a fast exploration of the hardware design space in order to provide guidance for selecting a suitable processing platform.
| Original language | English |
|---|---|
| Title of host publication | 2018 IEEE 13th International Symposium on Industrial Embedded Systems, SIES 2018 - Proceedings |
| Publisher | Institute of Electrical and Electronics Engineers |
| ISBN (Print) | 9781538641552 |
| DOIs | |
| Publication status | Published - 20 Aug 2018 |
| Event | 13th IEEE International Symposium on Industrial Embedded Systems, SIES 2018 - Graz, Austria Duration: 6 Jun 2018 → 8 Jun 2018 |
Conference
| Conference | 13th IEEE International Symposium on Industrial Embedded Systems, SIES 2018 |
|---|---|
| Country | Austria |
| City | Graz |
| Period | 6/06/18 → 8/06/18 |
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Keywords
- algorithm
- compiler
- data flow
- performance estimation
ASJC Scopus subject areas
- Computer Science Applications
- Hardware and Architecture
- Industrial and Manufacturing Engineering
Cite this
Generalized Execution Time Estimation. / Rechberger, Andreas; Brenner, Eugen.
2018 IEEE 13th International Symposium on Industrial Embedded Systems, SIES 2018 - Proceedings. Institute of Electrical and Electronics Engineers, 2018. 8442107.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Research › peer-review
}
TY - GEN
T1 - Generalized Execution Time Estimation
AU - Rechberger, Andreas
AU - Brenner, Eugen
PY - 2018/8/20
Y1 - 2018/8/20
N2 - While developing embedded devices a significant challenge is to choose the appropriate computing architecture. Especially during early design stages providing measurable metric on the performance demands to implement a specified algorithm is required. Usually this includes a large amount of target dependency, like the chosen micro-controller platform. This work aims on providing a generalized method to estimate the processing time of a dedicated algorithm, when being run on a variety of hardware choices. The focus is on a fast exploration of the hardware design space in order to provide guidance for selecting a suitable processing platform.
AB - While developing embedded devices a significant challenge is to choose the appropriate computing architecture. Especially during early design stages providing measurable metric on the performance demands to implement a specified algorithm is required. Usually this includes a large amount of target dependency, like the chosen micro-controller platform. This work aims on providing a generalized method to estimate the processing time of a dedicated algorithm, when being run on a variety of hardware choices. The focus is on a fast exploration of the hardware design space in order to provide guidance for selecting a suitable processing platform.
KW - algorithm
KW - compiler
KW - data flow
KW - performance estimation
UR - http://www.scopus.com/inward/record.url?scp=85053471690&partnerID=8YFLogxK
U2 - 10.1109/SIES.2018.8442107
DO - 10.1109/SIES.2018.8442107
M3 - Conference contribution
SN - 9781538641552
BT - 2018 IEEE 13th International Symposium on Industrial Embedded Systems, SIES 2018 - Proceedings
PB - Institute of Electrical and Electronics Engineers
ER -