As memories are becoming a ubiquitous and indispensable part of electronic devices across all industrial domains, the importance of their reliability and fault-tolerance increases. This especially holds for safety-critical applications, which exhibit different levels of data criticality. As a consequence, recent research aims to proactively engage environmentally induced soft errors, by developing new methods for error detection, mitigation, and data recovery in the mixed-critical memories. This article presents a flexible soft error correction strategy called Redundant Parity (RP), designed to enhance existing 1oo2 architectures. RP extends a 1oo2 system's ability of fault detection by enabling the recovery of faulty data utilizing the parity bit concept. An initial evaluation of the strategy in terms of its runtime performance and memory overhead is performed and compared with other software-based mitigation strategies. The preliminary results suggest that RP is indeed a suitable soft error mitigation strategy in existing 1oo2 fail-safe systems.
|Title of host publication||International Symposium on Software Reliability Engineering (ISSREW 2019)|
|Subtitle of host publication||Workshop on Software Hardware Interaction Faults (SHIFT 2019)|
|Number of pages||6|
|Publication status||Published - 2019|
- soft errors
Fields of Expertise
- Information, Communication & Computing
Kajmakovic, A., Diwold, K., Kajtazovic, N., & Zupanc, R. (2019). Flexible Soft error Mitigation Strategy for memories in mixed-critical systems. In International Symposium on Software Reliability Engineering (ISSREW 2019): Workshop on Software Hardware Interaction Faults (SHIFT 2019) IEEE Press.