Fixing Faults in VHDL-RTL Programs: An Application of Model-based Diagnosis to Digital Circuit Design

Bernhard Peischl, Franz Wotawa

Institute of Software Technology (7160)

Research output: Contribution to journal › Article

1 results

Finished
VHDL - Debugging VHDL Programs (DEV)
Peischl, B. J., Köb, D. & Wotawa, F.
1/11/01 → 31/08/04
Project: Research project