System level Electrostatic Discharges (ESD) can lead to soft-errors (e.g., bit-errors, wrong resets etc.). By this talk we try to offer guidance in finding the root cause of upsets frequently observed in immunity testing (e.g., ESD, EFT). At first a description of the ESD discharge process is given. It provides the necessary background for correctly analyzing ESD failures. Local scanning and in-circuit measurement techniques are explained. Further, it is shown how PCB scanning results, revealing local sensitivities, can be used for the characterization and optimization of circuit and ICs design and software for minimizing unwanted responses to soft-error causing noise. A series of measurements of such noise voltages coupled into a sensitive trace are presented.