Dynamic Scheduling for Efficient Hierarchical Sparse Matrix Operations on the GPU

Andreas Derler, Rhaleb Zayer, Hans-Peter Seidel, Markus Steinberger

Research output: Chapter in Book/Report/Conference proceedingConference paperpeer-review


We introduce a hierarchical sparse matrix representation (HiSparse) tailored for the graphics processing unit (GPU). The representation adapts to the local nonzero pattern at all levels of the hierarchy and uses reduced bit length for addressing the entries. This allows a smaller memory footprint than standard formats. Executing algorithms on a hierarchical structure on the GPU usually entails significant synchronization and management overhead or slowdowns due to diverging execution paths and memory access patterns. We address these issues by means of a dynamic scheduling strategy specifically designed for executing algorithms on top of a hierarchical matrix on the GPU. The evaluation of our implementation of basic linear algebra routines, suggests that our hierarchical format is competitive to highly optimized standard libraries and significantly outperforms them in the case of transpose matrix operations. The results point towards the viability of hierarchical matrix formats on massively parallel devices such as the GPU.
Original languageEnglish
Title of host publicationICS '17: Proceedings of the International Conference on Supercomputing
Place of PublicationNew York, NY, USA
ISBN (Print)978-1-4503-5020-4
Publication statusPublished - 2017
Externally publishedYes
EventInternational Conference on Supercomputing: ICS 2017 - Chicago, United States
Duration: 14 Jun 201716 Jun 2017


ConferenceInternational Conference on Supercomputing
Abbreviated titleICS '17
Country/TerritoryUnited States


  • GPU, hierarchical, linear algebra, sparse matrix


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