Debugging VHDL Designs Using Temporal Process Instances

Bernhard Peischl; Franz Wotawa; Daniel Köb

Debugging VHDL Designs Using Temporal Process Instances

Bernhard Peischl, Franz Wotawa, Daniel Köb

Institute of Software Technology (7160)

Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review

Original language	English
Title of host publication	Developments in Artificial Intelligence
Editors	Paul W. H. Chung, Chris Hinde, Moonis Ali
Place of Publication	Berlin, Heidelberg
Publisher	Springer
Pages	402-415
Volume	2718
ISBN (Print)	3-540-40455-4
Publication status	Published - 2003
Event	International Conference on Industrial and Engineering Applications of Artificial Intelligence and Expert Systems - Loughbourough, United Kingdom Duration: 23 Jun 2003 → 27 Jun 2003

Publication series

Name	Lecture notes in computer science : Lecture Notes in Artificial Intelligence
Publisher	Springer

Conference

Conference	International Conference on Industrial and Engineering Applications of Artificial Intelligence and Expert Systems
Country/Territory	United Kingdom
City	Loughbourough
Period	23/06/03 → 27/06/03

Treatment code (Nähere Zuordnung)

Basic - Fundamental (Grundlagenforschung)

VHDL - Debugging VHDL Programs (DEV)
Peischl, B. J., Köb, D. & Wotawa, F.
1/11/01 → 31/08/04
Project: Research project

Cite this

Debugging VHDL Designs Using Temporal Process Instances. / Peischl, Bernhard ; Wotawa, Franz; Köb, Daniel.
Developments in Artificial Intelligence. ed. / Paul W. H. Chung; Chris Hinde; Moonis Ali. Vol. 2718 Berlin, Heidelberg: Springer, 2003. p. 402-415 (Lecture notes in computer science : Lecture Notes in Artificial Intelligence).

Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review

Peischl, B , Wotawa, F & Köb, D 2003, Debugging VHDL Designs Using Temporal Process Instances. in PWH Chung, C Hinde & M Ali (eds), Developments in Artificial Intelligence. vol. 2718, Lecture notes in computer science : Lecture Notes in Artificial Intelligence, Springer, Berlin, Heidelberg, pp. 402-415, International Conference on Industrial and Engineering Applications of Artificial Intelligence and Expert Systems, Loughbourough, United Kingdom, 23/06/03.

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title = "Debugging VHDL Designs Using Temporal Process Instances",

author = "Bernhard Peischl and Franz Wotawa and Daniel K{\"o}b",

year = "2003",

language = "English",

isbn = "3-540-40455-4",

volume = "2718",

series = "Lecture notes in computer science : Lecture Notes in Artificial Intelligence",

publisher = "Springer",

pages = "402--415",

editor = "Chung, {Paul W. H.} and Chris Hinde and Moonis Ali",

booktitle = "Developments in Artificial Intelligence",

note = "International Conference on Industrial and Engineering Applications of Artificial Intelligence and Expert Systems ; Conference date: 23-06-2003 Through 27-06-2003",

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TY - GEN

T1 - Debugging VHDL Designs Using Temporal Process Instances

AU - Peischl, Bernhard

AU - Wotawa, Franz

AU - Köb, Daniel

PY - 2003

Y1 - 2003

M3 - Conference paper

SN - 3-540-40455-4

VL - 2718

T3 - Lecture notes in computer science : Lecture Notes in Artificial Intelligence

SP - 402

EP - 415

BT - Developments in Artificial Intelligence

A2 - Chung, Paul W. H.

A2 - Hinde, Chris

A2 - Ali, Moonis

PB - Springer

CY - Berlin, Heidelberg

T2 - International Conference on Industrial and Engineering Applications of Artificial Intelligence and Expert Systems

Y2 - 23 June 2003 through 27 June 2003

ER -

Debugging VHDL Designs Using Temporal Process Instances

Publication series

Conference

Treatment code (Nähere Zuordnung)

Projects

VHDL - Debugging VHDL Programs (DEV)

Cite this