Debugging VHDL Designs Using Temporal Process Instances

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Original languageEnglish
Title of host publicationDevelopments in Artificial Intelligence
EditorsPaul W. H. Chung, Chris Hinde, Moonis Ali
Place of PublicationBerlin, Heidelberg
PublisherSpringer
Pages402-415
Volume2718
ISBN (Print)3-540-40455-4
Publication statusPublished - 2003
EventInternational Conference on Industrial and Engineering Applications of Artificial Intelligence and Expert Systems - Loughbourough, United Kingdom
Duration: 23 Jun 200327 Jun 2003

Publication series

NameLecture notes in computer science : Lecture Notes in Artificial Intelligence
PublisherSpringer

Conference

ConferenceInternational Conference on Industrial and Engineering Applications of Artificial Intelligence and Expert Systems
CountryUnited Kingdom
CityLoughbourough
Period23/06/0327/06/03

Treatment code (Nähere Zuordnung)

  • Basic - Fundamental (Grundlagenforschung)

Projects

VHDL - Debugging VHDL Programs (DEV)

Peischl, B. J., Köb, D. & Wotawa, F.

1/11/0131/08/04

Project: Research project

Cite this

Peischl, B., Wotawa, F., & Köb, D. (2003). Debugging VHDL Designs Using Temporal Process Instances. In P. W. H. Chung, C. Hinde, & M. Ali (Eds.), Developments in Artificial Intelligence (Vol. 2718, pp. 402-415). (Lecture notes in computer science : Lecture Notes in Artificial Intelligence). Berlin, Heidelberg: Springer.