Debugging VHDL Designs Using Temporal Process Instances

Research output: Chapter in Book/Report/Conference proceedingConference contributionResearchpeer-review

Original languageEnglish
Title of host publicationDevelopments in Artificial Intelligence
EditorsPaul W. H. Chung, Chris Hinde, Moonis Ali
Place of PublicationBerlin, Heidelberg
PublisherSpringer
Pages402-415
Volume2718
ISBN (Print)3-540-40455-4
Publication statusPublished - 2003
EventInternational Conference on Industrial and Engineering Applications of Artificial Intelligence and Expert Systems - Loughbourough, United Kingdom
Duration: 23 Jun 200327 Jun 2003

Publication series

NameLecture notes in computer science : Lecture Notes in Artificial Intelligence
PublisherSpringer

Conference

ConferenceInternational Conference on Industrial and Engineering Applications of Artificial Intelligence and Expert Systems
CountryUnited Kingdom
CityLoughbourough
Period23/06/0327/06/03

Treatment code (Nähere Zuordnung)

  • Basic - Fundamental (Grundlagenforschung)

Cite this

Peischl, B., Wotawa, F., & Köb, D. (2003). Debugging VHDL Designs Using Temporal Process Instances. In P. W. H. Chung, C. Hinde, & M. Ali (Eds.), Developments in Artificial Intelligence (Vol. 2718, pp. 402-415). (Lecture notes in computer science : Lecture Notes in Artificial Intelligence). Berlin, Heidelberg: Springer.

Debugging VHDL Designs Using Temporal Process Instances. / Peischl, Bernhard; Wotawa, Franz; Köb, Daniel.

Developments in Artificial Intelligence. ed. / Paul W. H. Chung; Chris Hinde; Moonis Ali. Vol. 2718 Berlin, Heidelberg : Springer, 2003. p. 402-415 (Lecture notes in computer science : Lecture Notes in Artificial Intelligence).

Research output: Chapter in Book/Report/Conference proceedingConference contributionResearchpeer-review

Peischl, B, Wotawa, F & Köb, D 2003, Debugging VHDL Designs Using Temporal Process Instances. in PWH Chung, C Hinde & M Ali (eds), Developments in Artificial Intelligence. vol. 2718, Lecture notes in computer science : Lecture Notes in Artificial Intelligence, Springer, Berlin, Heidelberg, pp. 402-415, International Conference on Industrial and Engineering Applications of Artificial Intelligence and Expert Systems, Loughbourough, United Kingdom, 23/06/03.
Peischl B, Wotawa F, Köb D. Debugging VHDL Designs Using Temporal Process Instances. In Chung PWH, Hinde C, Ali M, editors, Developments in Artificial Intelligence. Vol. 2718. Berlin, Heidelberg: Springer. 2003. p. 402-415. (Lecture notes in computer science : Lecture Notes in Artificial Intelligence).
Peischl, Bernhard ; Wotawa, Franz ; Köb, Daniel. / Debugging VHDL Designs Using Temporal Process Instances. Developments in Artificial Intelligence. editor / Paul W. H. Chung ; Chris Hinde ; Moonis Ali. Vol. 2718 Berlin, Heidelberg : Springer, 2003. pp. 402-415 (Lecture notes in computer science : Lecture Notes in Artificial Intelligence).
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