Debugging VHDL Designs using Model-Based Reasoning

Research output: Contribution to journalArticleResearchpeer-review

Original languageEnglish
Pages (from-to)331-351
JournalArtificial Intelligence in Engineering
Volume14
Issue number4
DOIs
Publication statusPublished - 2000

Treatment code (Nähere Zuordnung)

  • Basic - Fundamental (Grundlagenforschung)

Cite this

Debugging VHDL Designs using Model-Based Reasoning. / Wotawa, Franz.

In: Artificial Intelligence in Engineering, Vol. 14, No. 4, 2000, p. 331-351.

Research output: Contribution to journalArticleResearchpeer-review

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