Automatic Fault Localization for Property Checking

Goerschwin Fey; Stefan Simon Staber; Roderick Paul Bloem; Rolf Drechsler

doi:10.1109/TCAD.2008.923234

Automatic Fault Localization for Property Checking

Goerschwin Fey, Stefan Simon Staber, Roderick Paul Bloem, Rolf Drechsler

Institute of Applied Information Processing and Communications (7050)

Research output: Contribution to journal › Article › peer-review

Abstract

We present an efficient fully automatic approach to fault localization for safety properties stated in linear temporal logic. We view the failure as a contradiction between the specification and the actual behavior and look for components that explain this discrepancy. We find these components by solving the satisfiability of a propositional Boolean formula. We show how to construct this formula and how to extend it so that we find exactly those components that can be used to repair the circuit for a given set of counterexamples. Furthermore, we discuss how to efficiently solve the formula by using the proper decision heuristics and simulation-based preprocessing. We demonstrate the quality and efficiency of our approach by experimental results

Original language	English
Pages (from-to)	1138-1149
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume	27
Issue number	6
DOIs	https://doi.org/10.1109/TCAD.2008.923234
Publication status	Published - 2008

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10.1109/TCAD.2008.923234

Formal Methods for Design & Verification
Jacobs, S., Bloem, R., Könighofer, R., Könighofer, B., Khalimov, A., Hofferek, G. & Braud-Santoni, N.
1/02/08 → 15/07/19
Project: Research area

Cite this

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AU - Staber, Stefan Simon

AU - Bloem, Roderick Paul

AU - Drechsler, Rolf

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AB - We present an efficient fully automatic approach to fault localization for safety properties stated in linear temporal logic. We view the failure as a contradiction between the specification and the actual behavior and look for components that explain this discrepancy. We find these components by solving the satisfiability of a propositional Boolean formula. We show how to construct this formula and how to extend it so that we find exactly those components that can be used to repair the circuit for a given set of counterexamples. Furthermore, we discuss how to efficiently solve the formula by using the proper decision heuristics and simulation-based preprocessing. We demonstrate the quality and efficiency of our approach by experimental results

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DO - 10.1109/TCAD.2008.923234

M3 - Article

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JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IS - 6

ER -

Automatic Fault Localization for Property Checking

Abstract

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Formal Methods for Design & Verification

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