Automated Debugging of Verilog Designs

Bernhard Peischl; Naveed Riaz; Franz Wotawa

doi:10.1142/S0218194012500209

Automated Debugging of Verilog Designs

Bernhard Peischl, Naveed Riaz, Franz Wotawa

Institute of Software Technology (7160)

Research output: Contribution to journal › Article › peer-review

Original language	English
Pages (from-to)	695-723
Journal	International Journal of Software Engineering and Knowledge Engineering
Volume	22
Issue number	5
DOIs	https://doi.org/10.1142/S0218194012500209
Publication status	Published - 2012

Fields of Expertise

Information, Communication & Computing

Treatment code (Nähere Zuordnung)

Basic - Fundamental (Grundlagenforschung)
Experimental

Access to Document

10.1142/S0218194012500209

Cite this

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title = "Automated Debugging of Verilog Designs",

author = "Bernhard Peischl and Naveed Riaz and Franz Wotawa",

year = "2012",

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language = "English",

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journal = "International Journal of Software Engineering and Knowledge Engineering ",

issn = "1793-6403",

publisher = "World Scientific ",

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TY - JOUR

T1 - Automated Debugging of Verilog Designs

AU - Peischl, Bernhard

AU - Riaz, Naveed

AU - Wotawa, Franz

PY - 2012

Y1 - 2012

UR - http://www.worldscientific.com/worldscinet/ijseke

U2 - 10.1142/S0218194012500209

DO - 10.1142/S0218194012500209

M3 - Article

SN - 1793-6403

VL - 22

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EP - 723

JO - International Journal of Software Engineering and Knowledge Engineering

JF - International Journal of Software Engineering and Knowledge Engineering

IS - 5

ER -

Automated Debugging of Verilog Designs

Fields of Expertise

Treatment code (Nähere Zuordnung)

Access to Document

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Cite this