Aspect ratio of radiation-hradened MOS transisotrs: Modelling of the equivalent channel dimensions of integrated MOS transistors in radiation-hardened enclosed layout

Research output: Contribution to journalSpecial issueResearchpeer-review

Abstract

The reliability of electronics in the proximity of the ionizing radiation is a key requirement in particular in high energy physics, nuclear power or space applications. One way to improve robustness of MOS transistors operating in such environments is to use enclosed layout techniques. This special layout approach helps to maintain leakage current of MOS transistors at low level even after irradiation, in contrast to a linear layout MOS transistor, where leakage current could increase by orders of magnitude. The issue, arising with enclosed layout transistors, is related to channel modelling, since the MOS transistor gate geometry is no more a simple rectangle. In this work, modelling of equivalent width and length dimensions of the MOS transistor channel under the gate is addressed. For this purpose transistors of four types and two layout versions, fabricated in a standard 180 nm CMOS process, are characterized. The accuracy of available models for equivalent channel dimensions is analysed, along with a new simplified geometrical model developed by the authors. They are further compared to the empirically extracted aspect ratio. The improvement possibilities for the considered models are then identified.
Original languageEnglish
Article number1613-7620
Number of pages8
Journale&i - Elektrotechnik und Informationstechnik
DOIs
Publication statusE-pub ahead of print - 17 Jan 2018

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Keywords

  • MOS transistor
  • radiation hardness
  • ionizing radiation
  • enclosed layout
  • aspect ratio

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Radiation
  • Modelling and Simulation

Fields of Expertise

  • Information, Communication & Computing

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