A comprehensive model of a clock line including large and small signal pin parameters, as well as channel parameters is presented. The small signal model allows analysis of in-band interference which can lead to soft failures, while large signal models allow for the simulation of current sharing between driver/receiver pin pairs.
|Journal||Electrical Overstress Electrostatic Discharge Symposium Proceedings|
|Publication status||Published - 26 Nov 2014|
|Event||36th International Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2014 - Tucson, United States|
Duration: 7 Sep 2014 → 12 Sep 2014
ASJC Scopus subject areas
- Electrical and Electronic Engineering