An architecture to enable on-chip cosimulation of ip-models with the apples gate-level accelerator

Alexander Maili, Christian Steger, Reinhold Weiß, Damian Dalton

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Original languageEnglish
Title of host publicationTelecommunications and Mobile Computing [Elektronische Ressource]
Publisher.
Publication statusSubmitted - 2005

Projects

Hardware/Software-Codesign

Pieber, T. W., Steger, C., Weiß, R., Ulz, T., Schachner, M., Kreiner, C. J., Plank, H., Troyer, M., Gressl, L. A., Seifert, C., Warmer, F., Rech, A., Erb, M., Scherr, F., Kammerer, M., Stelzer, P., Frewein, A., Strasser, A., Lindner, J., Ess, A., Feldbacher, M. & Weissteiner, H.

1/01/95 → …

Project: Research area

Cite this

Maili, A., Steger, C., Weiß, R., & Dalton, D. (2005). An architecture to enable on-chip cosimulation of ip-models with the apples gate-level accelerator. Manuscript submitted for publication. In Telecommunications and Mobile Computing [Elektronische Ressource] ..