An application of system level efficient ESD design for high- speed USB3.x interface

Pengyu Wei, Giorgi Maghlakelidze, Jianchi Zhou, Harald Gossner, David Pommerenke

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A high-speed USB3.x IO is analyzed using the System level efficient ESD design methodology [1] using on-board current and voltage measurements for the TX and RX pins. The interactions between external ESD protection device and the on-chip ESD protection circuit is investigated in measurement and simulation.

Original languageEnglish
Title of host publicationElectrical Overstress/Electrostatic Discharge Symposium Proceedings, EOS/ESD 2018
PublisherESD Association
ISBN (Electronic)1585373028
Publication statusPublished - 25 Oct 2018
Externally publishedYes
Event40th Annual Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2018 - Reno, United States
Duration: 23 Sep 201828 Sep 2018

Publication series

NameElectrical Overstress/Electrostatic Discharge Symposium Proceedings
Volume2018-September
ISSN (Print)0739-5159

Conference

Conference40th Annual Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2018
CountryUnited States
CityReno
Period23/09/1828/09/18

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Wei, P., Maghlakelidze, G., Zhou, J., Gossner, H., & Pommerenke, D. (2018). An application of system level efficient ESD design for high- speed USB3.x interface. In Electrical Overstress/Electrostatic Discharge Symposium Proceedings, EOS/ESD 2018 (Electrical Overstress/Electrostatic Discharge Symposium Proceedings; Vol. 2018-September). ESD Association.