A temperature analysis for NFC-powered smart lab-on-chip devices

Carolin Kollegger, Christoph Steffan, Philipp Greiner, Clemens Rabl, David Lugitsch, Gerald Holweg, Bernd Deutschmann

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a temperature analysis for NFC-powered Lab-on-Chip (LoC) solutions. It is based on a monolithically implemented LoC and uses a 130 nm standard CMOS process. The LoC has an active chip area of 6.24 mm 2 . An application-independent temperature gathering mesh is implemented on the chip substrate. It allows a real time NFC-caused temperature analysis. Measurement data regarding heat spreading, the influence of the glob top, and the effect of the PCB layout is presented. A warming reduction from 23.05°C to 3.8°C using the same power source is achieved. Detailed data on the temperature gradient over time for warming and cooling is also provided.

Original languageEnglish
Title of host publication2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018
PublisherInstitute of Electrical and Electronics Engineers
Pages1058-1061
Number of pages4
Volume2018-August
ISBN (Electronic)9781538673928
DOIs
Publication statusPublished - 22 Jan 2019
Event61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018 - Windsor, Canada
Duration: 5 Aug 20188 Aug 2018

Conference

Conference61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018
CountryCanada
CityWindsor
Period5/08/188/08/18

Keywords

  • 130 nm
  • CMOS
  • Lab-on-chip
  • NFC

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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