A Systematic Method to Characterize the Soft-Failure Susceptibility of the I/Os on an Integrated Circuit Due to Electrostatic Discharge

Benjamin J. Orr; Sebastian Koch; Harald Gossner; David J. Pommerenke

doi:10.1109/TEMC.2018.2890704

A Systematic Method to Characterize the Soft-Failure Susceptibility of the I/Os on an Integrated Circuit Due to Electrostatic Discharge

Benjamin J. Orr^*, Sebastian Koch, Harald Gossner, David J. Pommerenke

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

Abstract

In this paper, we present a methodology to characterize the I/O pins of a logic IC such as an application processor or ASIC with respect to soft-failure susceptibility due to electrostatic discharge. With the IC in a functional system, variable stress pulses are injected while the interface under test operates in real-world use cases. This test methodology enables the extraction of the IC behavior during ESD-like stress on a pin-by-pin basis. This characterization is intended to be performed during the validation stages of component development, making it possible to provide system developers with valuable information about potential modes of failure. This early detection of potential soft errors and their sensitivities can then be used to design for soft-failure robustness from the very beginning of system hardware and software design.

Original language	English
Article number	8844106
Pages (from-to)	16-24
Number of pages	9
Journal	IEEE Transactions on Electromagnetic Compatibility
Volume	62
Issue number	1
DOIs	https://doi.org/10.1109/TEMC.2018.2890704
Publication status	Published - 1 Feb 2020
Externally published	Yes

Keywords

Electrostatic interference
fault tolerance
immunity testing
integrated circuit reliability
system-on-chip

ASJC Scopus subject areas

Atomic and Molecular Physics, and Optics
Condensed Matter Physics
Electrical and Electronic Engineering

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10.1109/TEMC.2018.2890704

Cite this

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A Systematic Method to Characterize the Soft-Failure Susceptibility of the I/Os on an Integrated Circuit Due to Electrostatic Discharge

Abstract

Keywords

ASJC Scopus subject areas

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