In this paper a simple technique to use standard digital CMOS logic cells from 80mV to 1.2V is presented. By applying a compensation network process-related variations of the logic’s switching threshold can be reduced by 89% for a given supply voltage. Therefore post-fabrication process steps can be avoided. The principle is introduced by a simple inverter gate and expanded to more complex NAND, NOR and Flip-Flop cells. A test chip has been fabricated in a 130nm process proving the functionality of the proposed digital cells.
|Number of pages||4|
|Publication status||Published - 2013|
|Event||IEEE International Symposium on Circuits and Systems: ISCAS 2013 - Beijing, China|
Duration: 19 May 2013 → 23 May 2013
|Conference||IEEE International Symposium on Circuits and Systems|
|Period||19/05/13 → 23/05/13|