A Process-Variation Compensation Scheme to Operate CMOS Digital Logic Cells in Deep Sub-Threshold Region at 80mV

Robert Kappel, Mario Auer, Wolfgang Pribyl, Guenter Hofer, Gerald Holweg

Research output: Contribution to conferencePaper

Abstract

In this paper a simple technique to use standard digital CMOS logic cells from 80mV to 1.2V is presented. By applying a compensation network process-related variations of the logic’s switching threshold can be reduced by 89% for a given supply voltage. Therefore post-fabrication process steps can be avoided. The principle is introduced by a simple inverter gate and expanded to more complex NAND, NOR and Flip-Flop cells. A test chip has been fabricated in a 130nm process proving the functionality of the proposed digital cells.
Original languageEnglish
Pages562-565
Number of pages4
Publication statusPublished - 2013
EventInternational Symposium on Circuits and Systems (ISCAS) - Beijing, China
Duration: 19 May 201323 May 2013
http://ieee-cas.org/pubs/tcsvt/iscas-2013

Conference

ConferenceInternational Symposium on Circuits and Systems (ISCAS)
CountryChina
CityBeijing
Period19/05/1323/05/13
Internet address

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    Kappel, R., Auer, M., Pribyl, W., Hofer, G., & Holweg, G. (2013). A Process-Variation Compensation Scheme to Operate CMOS Digital Logic Cells in Deep Sub-Threshold Region at 80mV. 562-565. Paper presented at International Symposium on Circuits and Systems (ISCAS), Beijing, China.