A novel method for ESD soft error analysis on integrated circuits using a TEM cell

Jongsung Lee*, Jaedeok Lim, Byongsu Seol, Zhen Li, David Pommerenke

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The ultimate goal of this work is to predict ESD system level behavior. A methodology which can evaluate the IC immunity in terms of ESD-induced soft error is introduced. A modified TEM cell and a simple test board with a memory IC are designed for this purpose. The correlation between product level ESD standard test and the proposed IC immunity test is discussed.

Original languageEnglish
Title of host publicationElectrical Overstress/Electrostatic Discharge Symposium Proceedings 2012, EOS/ESD 2012
Publication statusPublished - 27 Nov 2012
Externally publishedYes
Event34th International Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2012 - Tucson, AZ, United States
Duration: 9 Sep 201214 Sep 2012

Publication series

NameElectrical Overstress/Electrostatic Discharge Symposium Proceedings
ISSN (Print)0739-5159

Conference

Conference34th International Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2012
CountryUnited States
CityTucson, AZ
Period9/09/1214/09/12

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Lee, J., Lim, J., Seol, B., Li, Z., & Pommerenke, D. (2012). A novel method for ESD soft error analysis on integrated circuits using a TEM cell. In Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2012, EOS/ESD 2012 [6333316] (Electrical Overstress/Electrostatic Discharge Symposium Proceedings).