Abstract
This document proposes a new methodology to measure the voltage-dependent behavior of parasitic capacitances of super junction power MOSFETs. The measurement technique allows to extract all parasitic elements (capacitances and inductances) with only one measurement while a variable DC voltage is applied between the drain and source pin of the super junction MOSFET. The results can be used to create simulation models of MOSFETs and possibly complete power modules, that accurately represent their high frequency behavior to solve electromagnetic compatibility (EMC) problems in transient simulators, such as LTspice.
| Original language | English |
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| Title of host publication | 2019 21st European Conference on Power Electronics and Applications, EPE 2019 ECCE Europe |
| Publisher | Institute of Electrical and Electronics Engineers |
| ISBN (Electronic) | 9789075815313 |
| DOIs | |
| Publication status | Published - Sept 2019 |
| Event | 21st European Conference on Power Electronics and Applications, ECCE Europe: EPE 2019 - Genova, Italy Duration: 3 Sept 2019 → 5 Sept 2019 |
Conference
| Conference | 21st European Conference on Power Electronics and Applications, ECCE Europe |
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| Country/Territory | Italy |
| City | Genova |
| Period | 3/09/19 → 5/09/19 |
Keywords
- Capacitance Measurement
- EMC
- Power MOSFET
- S-parameter Meassurement
- Spice Model
ASJC Scopus subject areas
- Mechanical Engineering
- Electronic, Optical and Magnetic Materials
- Control and Optimization
- Energy Engineering and Power Technology
- Electrical and Electronic Engineering