A Hierarchical Pre-Layout Power Integrity Simulation Flow for Mixed Signal & RF Integrated Circuits

Martin Unterweissacher

Research output: ThesisDoctoral ThesisResearch

Original languageGerman
Publication statusPublished - 2009

Cite this

A Hierarchical Pre-Layout Power Integrity Simulation Flow for Mixed Signal & RF Integrated Circuits. / Unterweissacher, Martin.

2009.

Research output: ThesisDoctoral ThesisResearch

@phdthesis{91402a9b7078404e92b7bc736f571cb0,
title = "A Hierarchical Pre-Layout Power Integrity Simulation Flow for Mixed Signal & RF Integrated Circuits",
author = "Martin Unterweissacher",
year = "2009",
language = "deutsch",

}

TY - THES

T1 - A Hierarchical Pre-Layout Power Integrity Simulation Flow for Mixed Signal & RF Integrated Circuits

AU - Unterweissacher, Martin

PY - 2009

Y1 - 2009

M3 - Dissertation

ER -