A Full Gate-timing Hardware Simulator

Christian Steger, Damian Dalton, Abhay Vadher

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Original languageEnglish
Title of host publicationAustrochip
Publisher.
Publication statusSubmitted - 2002

Projects

Hardware/Software-Codesign

Pieber, T. W., Steger, C., Weiß, R., Ulz, T., Schachner, M., Kreiner, C. J., Plank, H., Troyer, M., Gressl, L. A., Seifert, C., Warmer, F., Rech, A., Erb, M., Scherr, F., Kammerer, M., Stelzer, P., Frewein, A., Strasser, A., Lindner, J., Ess, A., Feldbacher, M. & Weissteiner, H.

1/01/95 → …

Project: Research area

Cite this

Steger, C., Dalton, D., & Vadher, A. (2002). A Full Gate-timing Hardware Simulator. Manuscript submitted for publication. In Austrochip ..