A circuit model for ESD performance analysis of printed circuit boards

Byong Su Seol*, Jong Sung Lee, Jae Deok Lim, Hyungseok Lee, Harkbyeong Park, Argha Nandy, David Pommerenke

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference paperpeer-review

Abstract

This paper provides a SPICE-eompatible circuit model for characterizing electrostatic discharge (ESD) clamping performance of protection devices mounted on printed circuit boards (PCBs). An equivalent circuit model for a commercial ESD generator is introduced and a simulation methodology of an ESD protection device with non-linear resistance characteristic using voltage controlled current source is described. These models combined to create a full circuit model with a PCB model in a SPICE-like circuit simulator. Comparison results between the simulated and measured are presented to verify the accuracy of the proposed circuit model. A trade-off analysis between the ESD clamping performance and signal integrity with the ESD protection device in high-speed applications is also presented as a case study.

Original languageEnglish
Title of host publication2008 Electrical Design of Advanced Packaging and Systems Symposium, IEEE EDAPS 2008 - Proceedings
Pages120-123
Number of pages4
DOIs
Publication statusPublished - 1 Dec 2008
Externally publishedYes
Event2008 Electrical Design of Advanced Packaging and Systems Symposium, IEEE EDAPS 2008 - Seoul, Korea, Republic of
Duration: 10 Dec 200812 Dec 2008

Publication series

Name2008 Electrical Design of Advanced Packaging and Systems Symposium, IEEE EDAPS 2008 - Proceedings

Conference

Conference2008 Electrical Design of Advanced Packaging and Systems Symposium, IEEE EDAPS 2008
Country/TerritoryKorea, Republic of
CitySeoul
Period10/12/0812/12/08

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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