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Publication Year

  • 2020
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Author

  • Tobias Peter Scheipel
2017

Einheit zur anwendungsbezogenen Leistungsmessung für die RISC-V-Architektur

Scheipel, T. P., Mauroner, F. & Baunach, M. C., 2017, Logistik und Echtzeit. Springer Verlag, p. 69-78 (Informatik aktuell).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

System-Aware Performance Monitoring Unit for RISC-V Architectures

Scheipel, T. P., Mauroner, F. & Baunach, M. C., 31 Aug 2017, Proceedings of the 20th Euromicro Conference on Digital System Design (DSD).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2018
2020

FPGA-Based Debugging with Dynamic Signal Selection at Run-Time

Fiala, G., Scheipel, T. P., Neuwirth, W. & Baunach, M. C., 1 Jan 2020, 17th Workshop on Automotive Software Engineering (ASE 2020). 7 p. (CEUR Workshop Proceedings; vol. 2581).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Open Access

papagenoX: Generation of Electronics and Logic for Embedded Systems from Application Software

Scheipel, T. P. & Baunach, M. C., 28 Feb 2020, 9th International Conference on Sensor Networks . INSTICC – Institute for Systems and Technologies of Information, Control and Communication, Vol. 1. p. 136-141

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Open Access