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Publication Year

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Author

  • Tobias Peter Scheipel
2017

Einheit zur anwendungsbezogenen Leistungsmessung für die RISC-V-Architektur

Scheipel, T. P., Mauroner, F. & Baunach, M. C., 2017, Logistik und Echtzeit. Springer Verlag, p. 69-78 (Informatik aktuell).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

System-Aware Performance Monitoring Unit for RISC-V Architectures

Scheipel, T. P., Mauroner, F. & Baunach, M. C., 31 Aug 2017, Proceedings of the 20th Euromicro Conference on Digital System Design (DSD).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2018
2019

papagenoPCB: An Automated Printed Circuit Board Generation Approach for Embedded Systems Prototyping

Scheipel, T. P. & Baunach, M. C., 24 Mar 2019, ICONS 2019 - The Fourteenth International Conference on Systems. p. 20-25 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Open Access