Secure High Speed Communications (Sichere Kommunikation bei hohen Geschwindigkeiten)

Project: Research project

Project Details


The main goals of the project have been centered around high
speed implementations of public key cryptography. In
particular, three threads have been investigated:
(1) the development of appropriate hardware algorithms,
(2) the verification of these algorithms by using suitable
methods for VLSI implementation, and
(3) to design, manufacture, and test integrated circuits
resulting from (1) and (2).

We have chosen two basic routes to achieve this. On the
first route we have designed and implemented a series of RSA
encryption/decryption chips with the goal of reaching an
encryption speed of 200 kbits/sec. The second route has
also the goal to propose a system for high speed public
key cryptography, but with a different underlying
arithmetic system, the residue number system.
On this route, we have designed two chips which serve
as the basic units in a massively parallel system.
Effective start/end date1/04/9331/03/96


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