PUMA - Power Management solutions for Next Generation Mobile Applications

  • Jackum, Thomas, (Co-Investigator (CoI))
  • Maderbacher, Gerhard, (Co-Investigator (CoI))
  • Santa, Thomas, (Co-Investigator (CoI))
  • Pribyl, Wolfgang (Principal Investigator (PI))

Project: Research project

Project Details


The size scaling in the CMOS technology is predicted to stagnate towards the end of the decade. Only
the SoC integration has the potential to continue IC cost reduction and to perpetuate growth in the
product functionality. Thus there is a strong need to integrate PMUs for future mobile devices on a
SoC, and for cost and form factor reasons use the latest deep submicron standard CMOS
technologies. Innovation is required on a wide front in technology and device side (e.g. high voltage
MOS devices, high voltage capacitors), as well as on system and circuit level. The driving factors,
such as minimising standby currents at low/no load, reducing the number of external devices,
enhancing safe battery operation and making use of deep-submicron advantages and standard CMOS
without extra cost constitute the goals of the PUMA project. It is possible to achieve these goals only
by integrating the PMU on the same chip as the power consumers and thus the development aimed at
is integrating the PMU as an inherent part of the SoC. The target is to transform the PMU, which in a
state-of-the-art solution is a separate entity usually on a separate chip, as a part of the 45nm SoC.
When integrating the PMU in a SoC a challenge is the possible interference to RF modules that are
integrated on the same SoC. This can be overcome by carefully analysing layout issues and defining
guidelines for the top level integration of a PMU in a SoC containing RF sensible block, defining
frequency planning techniques to avoid interference at critical frequencies and investigating switching
interference mitigation techniques.
Effective start/end date1/04/0831/12/10