Adding security to devices with limited computational requirements remains a challenging problem, and very little research has been done to design lightweight, low-power HW architectures for Lattice-based Post-Quantum Cryptography (PQC). Platform and application-specific optimization also plays an important role in making PQC available for deployment on a wide variety of platforms, and security against side-channel and fault attacks is also required depending on the application domain. Very few studies were carried out on the design and implementation of efficient countermeasures on HW platforms to protect lattice-based PQC. This project is a step in taking PQC beyond NIST standardization and preparing it for real deployment.
|Effective start/end date||1/06/21 → 31/05/24|