Modern societies rely on vast numbers of trusted services in such diverse fields as infrastructure, transportation or the financial markets. Most of these services rely on computer-based information systems, composed of stationary as well as an increasing number of mobile devices. All of these devices are required to assure security, dependability and trust for their prospective users.
However, a growing number of increasingly refined higher-order fault attacks (FA) aim at extracting sensitive information from these systems. Furthermore, the technological trends towards high-level integration come at the cost of increased susceptibility to random faults. For this reason, gradually more complex fault detection and recovery mechanisms have to be integrated also into mobile trusted devices.
Especially for mobile devices operating on limited power budgets (e.g., battery powered or energy harvesting devices), a trade-off between the effectiveness and the power consumption impact of fault attack detection / recovery mechanisms has to be found. Trusted systems hardware and software developers are still lacking effective development methodologies and tools for exploring this trade-off.
Cost and time-to-market pressure are economical drivers for establishing development methodologies and tools that ensure short design cycles. The constantly increasing complexity of mobile trusted devices in recent years further increases the development effort.
The goal of the POWER-MODES project is to provide key innovations in hybrid fault attack and power emulation: (1) Integration of higher-order fault attack emulation and power emulation approach alongside state-of-the art functional emulation to enable rapid fault attack-aware and power-aware trusted system development, (2) power-effectiveness analysis and optimization of fault attack detection and recovery techniques in the development process of the trusted system, and (3) development, implementation and fabrication of fault attack resistant operating system for RF-powered smart cards. It is expected that the proposed approach dramatically increases the possibilities for fault attack- and power-aware development compared to existing commercial solutions. Furthermore, the overhead introduced by the joint fault attack and power emulation approach is likely to be compensated by the added value of the tool chain.