JavaCards are pocket-sized computers supporting platform independent Java applets. They are commonly used for high security relevant applications like banking, e-government, and transport identification. Therefore they have to support advanced security functionality and have to be developed very carefully. Furthermore these use cases require a high computation performance to achieve transaction processing times of down to 100 ms.
This proposed PhD thesis concentrates on high-performance security features on the architecture and microarchitecture layer of JavaCard architectures. This includes the embedded software (on different layers: Java application layer, Java operating system layer, and native operating system layer) and security relevant parts of the JavaCard hardware architecture itself. It does not include well standardized cryptographic algorithms. A HW/SW codesign methodology will be developed that is able to provide sufficient information for a design space evaluation in respect to security and performance. Using this environment different security mechanisms and architectures will be modelled and evaluated in several phases beginning with a well known existing JavaCard system. This will result in a proof-of-concept prototype (implemented on an FPGA) of a new architecture based on the new results in secure high-performance system architectures.
The codesign environment will be based on Transaction Level Modelling with SystemC. This allows flexible and fast simulation of hardware and software components of the system. Additional behavioural information will be integrated into the model to allow timing and power analysis. Fault injection will be used for attack simulation to guarantee the secureness of the system.