GRANDESCA - Generating RANDom values for Encryption in the presence of Side Channel and other Attacks

  • Aigner, Manfred Josef, (Co-Investigator (CoI))
  • Kirschbaum, Mario, (Co-Investigator (CoI))
  • Popp, Thomas, (Principal Investigator (PI))

Project: Research project

Description

Most cryptographic algorithms and devices need a reliable source of random numbers to work in a secure manner. For example, the cipher key used in an encryption algorithm must be random. Generating random numbers with digital hardware is quite a challenging task and requires a lot of expertise in that field. Although there are several problems known for state-of-the-art concepts for random number generators (RNGs) in digital hardware, the risk when introducing new approaches for RNGs is very high. Therefore, a significant amount of research is necessary when proposing new concepts for RNGs in digital hardware to avoid weaknesses in this crucial cryptographic component.

Cryptographic devices also need random values if they are protected against power analysis attacks with the help of randomization countermeasures. Power analysis attacks allow to retrieve information about secret data like the cipher key by analyzing the power consumption while the device processes this secret data. Cryptographic devices are made resistant against such attacks by breaking the correlation between the processed data and the power consumption. Randomization countermeasures achieve this decorrelation for example by shuffling the execution order of algorithms, masking the processed intermediate values with random numbers, or producing noise that conceals the interesting information in the power consumption. In the last years, various logic styles that work with masked intermediate values have been proposed. Weaknesses of these masked logic styles have been identified only recently and need further investigantions.

Within the project GRANDESCA, radical new concepts for random number generation are proposed and investigated. Furthermore, the open issues of masked logic styles are analyzed by means of proptotype chips and simulations. This should help to improve the resistance of these masked logic styles against power analysis attacks.
StatusFinished
Effective start/end date1/02/0731/01/09