EU - TAMPRES - TAMper Resistant Sensor node

  • Hutter, Michael, (Co-Investigator (CoI))
  • Kirschbaum, Mario, (Co-Investigator (CoI))
  • Plos, Thomas, (Co-Investigator (CoI))
  • Korak, Thomas, (Co-Investigator (CoI))
  • Wenger, Erich, (Co-Investigator (CoI))
  • Schmidt, Jörn-Marc, (Principal Investigator (PI))

Project: Research project

Project Details


As the Internet of Things becomes a reality the trustworthiness of all its components assumes the utmost importance. The trustworthiness of any system in the definition of call 5 i.e. security, reliability etc. depends on its weakest part. When wireless sensor nodes (WSN) are included in the Internet of Things then it is likely that one of the more vulnerable parts will be the wireless sensor nodes themselves. These devices can be attacked by standard network based approaches but also by physical means if they are left unattended in remote sites which is, after all, the preferred application for WSN. While much research effort has been spent on improving the network security of WSN, the protection of the nodes and especially their protection against physical attacks has been, until now, neglected. We are convinced that protecting the wireless sensor nodes is essential since compromised nodes put the whole system at risk.
TAMPRES aims to significantly improve the trustworthiness of wireless sensor nodes. To achieve this goal we will investigate protection mechanisms in the following areas:
Prevention of side-channel and fault-injection attacks: evaluation and development of appropriate counter measures while also considering the severe constraints of energy and silicon area.
Provision of flawless implementation of light-weight cryptographic cores: development of secure
and properly implemented light-weight cryptographic cores to provide uncompromised
cryptographic strength to higher layers.
Attack resistant system architecture: secure integration and partitioning of the whole system
including hardware components and secure low level services.
The range of protection mechanisms available will be evaluated by experiments with existing and recently
manufactured ASICs. To ensure manufacturer independence, both the NXP and the IHP technology will be
used to evaluate the results. TAMPRES will also integrate its findings in a methodology which supports
system designers to select the correct means to protect their new devices.

Coordinator: IHP GmbH/ Leibniz Institut für innovative Mikroelektronik
Effective start/end date1/10/1030/09/13