Christian Vogel

Priv.-Doz. Dipl.-Ing. Dr.techn.

20002018

Research output per year

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Research Output

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2010

A Signal Processing View on Time-interleaved ADCs

Vogel, C., 2010, Analog Circuit Design. Roermund, A. H. M., Casier, H. & Steyaert, M. (eds.). 1 ed. Springer, p. 61-78

Research output: Chapter in Book/Report/Conference proceedingChapter